MC100LVEL29

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?ECL Dual Differential Clock/Data D Flip-Flop with Set and Reset

制造商：ON

中文數(shù)據(jù)手冊

產(chǎn)品信息

The MC100LVEL29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC100LVEL29 is pin and functionally equivalent to the MC100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.
The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to V
and the Dbar input will bias around V
/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.
Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.
The V
pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
as a switching reference voltage. V
may also rebias AC coupled inputs. When used, decouple V
and V
via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
should be left open.

1100MHz Flip-Flop Toggle Frequency
ESD Protection: >2 KV HBM
580 ps Typical Propagation Delays
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
= 3.0 V to 3.8 V with V
= 0 V
NECL Mode Operating Range: V
= 0 V with V
= -3.0 V to -3.8 V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Flammability Rating: UL-94 code V-0 @ 1?", Oxygen Index 28 to 34
Transistor Count = 313 devices
Pb-Free Packages are Available

電路圖、引腳圖和封裝圖

MC100LVEL29電路圖

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型號	制造商	描述	購買
MC100LVEL29DWG	ON		立即購買
MC100LVEL29DWR2G	-	-	立即購買

技術(shù)資料

標(biāo)題	類型	大?。↘B）	下載
AC Characteristics of ECL Devices	PDF	896	點擊下載
ECL Clock Distribution Techniques	PDF	54	點擊下載
Interfacing Between LVDS and ECL	PDF	121	點擊下載
Designing with PECL (ECL at +5.0 V)	PDF	102	點擊下載
The ECL Translator Guide	PDF	142	點擊下載
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	PDF	90	點擊下載
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	PDF	71	點擊下載
Storage and Handling of Drypack Surface Mount Device	PDF	49	點擊下載

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