描述The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eightTMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 deviceprovides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packetprocessing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06device is optimal for embedded infrastructure applications like cloud computing, media processing,high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.The C66x core combines fixed-point and floating-point computational capability in theprocessor without sacrificing speed, size, or power consumption. The raw computational performanceis 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100%backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructionstargeted for floating point (FPi) and vector math oriented (VPi) processing.The 66AK2H14/12/06 device has a complete set of development tools that includes: a Ccompiler, an assembly optimizer to simplify programming and scheduling, and aWindows? debugger interface forvisibility into source code execution.特性 Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core38.4 GMacs/Core for Fixed Point @ 1.2 GHz19.2 GFlops/Core for Floating Point @ 1.2 GHzMemory32-KB L1P Per CorePac32-KB L1D Per CorePac1024-KB Local L2 Per CorePacARM CorePac Four ARM? Cortex?-A15 MPCore? Processors at up to 1.4 GHz 4MB of L2 Cache Memory Shared by Four ARM Cores Full Implementation of ARMv7-A Architecture Instruction Set 32-KB L1 Instruction and Data Caches per Core AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC forLow-Latency Access to Shared MSMC SRAMMulticore Shared Memory Controller (MSMC)6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac Memory Protection Unit (MPU) for Both MSM SRAM andDDR3_EMIFMulticore Navigator16k Multipurpose Hardware Queues With Queue Manager Packet-Based DMA for Zero-OverheadTransfers Network CoprocessorPacket Accelerator Enables Support for Transport Plane IPsec, GTP-U, SCTP, PDCPL2 User Plane PDCP (RoHC, Air Ciphering)1-Gbps Wire Speed Throughput at 1.5 MPackets PerSecondSecurityAccelerator Engine Enables Support for IPSec, SRTP, 3GPP, and WiMAX Air Interface, andSSL/TLS SecurityECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES,Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5Up to 2.4 Gbps IPSec and 2.4Gbps Air CipheringEthernet Subsystem Five-Port Switch (Four SGMIIPorts)Peripherals Four Lanes of SRIO 2.1Supports up to 5 GBaudSupports Direct I/O, Message PassingTwo Lanes PCIe Gen2Supports up to 5 GBaudTwo HyperLinksSupports Connections to Other KeyStone? Architecture Devices ProvidingResource ScalabilitySupports up to 50 GBaud10-Gigabit Ethernet (10-GbE) Switch Subsystem(66AK2H14 Only)Two XFI PortsIEEE 1588 SupportFive Enhanced Direct Memory Access (EDMA) Modules Two 72-Bit DDR3 Interfaces With Speeds up to 1600 MHz EMIF16 Interface USB 3.0 Two UART Interfaces Three I2C Interfaces32 GPIO PinsThree SPI InterfacesSemaphore Module 64-Bit TimersTwenty 64-Bit Timers for 66AK2H14 and66AK2H12Fourteen 64-Bit Timers for 66AK2H06 Five On-Chip PLLsCommercial Case Temperature:0oC to85oC Extended Case Temperature:–40oC to 100oCAll trademarks are the property of their respective owners.